The present invention relates to a system and method for recovering energy in power converters. In particular, the invention provides a circuit and method for recovering energy using a circuit having synchronous rectifiers.
DC to DC (DC/DC) voltage converters provide a regulated DC output voltage to electronic devices and circuits from a different level DC input voltage. In the creation of an output DC voltage signal from the input voltage signal, power is invariably lost.
Generally, it is a goal to reduce power losses in a converter, thereby improving the efficiency of the converter and to improve thermal performance, i.e. have a tolerable operating temperature for the converter.
Power losses may be reduced by utilizing synchronous rectifiers in the output stage of the converter. Synchronous rectifiers are output rectifier circuits comprising low Rds-on FETs in parallel with Schottky diodes at each output terminal. Each Schottky diode prevents the body diode of the synchronous rectifier from turning on when the FET is off. The FET is turned on by a control circuit connected to its gate when current flows in the forward direction of its parallel Schottky diode. However, in order for the synchronous rectifier to be effective, the on voltage drop of the FET at full load current must be less than that of the Schottky diode forward drop. This enables current to flow through the FET and not through the Schottky diode when the FET is on. Accordingly, the synchronous rectifier provides a lower voltage drop than the typical 0.3 volt drop associated with Schottky diodes, thus improving the efficiency.
General background on known methods of improving power loss in circuits is found in xe2x80x9cConduction Power Loss in MOSFET Synchronous Rectifier with Parallel-Connected Schottky Barrier Diodexe2x80x9d in IEEE Transactions on Power Electronics Vol. 13, No 4, July 1998 which is incorporated into this application by reference.
However there remains a need for more efficient circuits in DC/DC converters to reduce power losses.
In a first aspect, the invention provides a power loss reduction circuit for use in an output stage of a voltage converter. The output stage has an output winding having first and second output terminals. The output stage produces an alternating cyclic signal at the first output terminal and a second complementary alternating cyclic output signal at the second output terminal. The circuit has one transistor with a conduction path associated with the first output terminal and ground. The transistor has a control terminal to regulate a first signal flowing through the conduction path by a first control signal. Also the transistor has a lower voltage drop in its conduction path than one for a Schottky diode. There is also a clamping circuit associated with the first output terminal for reducing a ringing signal present on the first signal when the first alternating cyclic signal becomes positive. There is also a second transistor with a second conduction path associated with the second output terminal and ground. The second transistor has a second control terminal to regulate a second signal flowing through its conduction path by a second control signal. The second transistor has a lower voltage drop in its second conduction path than one for a Schottky diode. There is also a second clamping circuit associated with the second output terminal for reducing another ringing signal present on the second signal when the second alternating cyclic signal becomes positive. There is also an energy storage device associated with the first and second clamping circuits to store energy from the first and second ringing signals.
The power loss reduction circuit may have diodes in the first and second clamping circuits. Further, the circuit may use a capacitor for the energy storage device and may use FETs for the first and second transistors. Further the FETs may be MOSFETs.
The power loss reduction circuit may use energy stored in the capacitor to drive the first and second transistors.
The power loss reduction circuit may further have a third transistor connected in parallel with the first transistor and a fourth transistor connected in parallel with the second transistor. The third transistor is controlled by the first control signal and the fourth transistor controlled by the second control signal. The third and fourth transistors may be FETs.
The power loss reduction circuit may have the output winding and the first and second output terminal arranged in a center tap configuration.
The power loss reduction circuit may have the output winding and the first and second output terminal arranged in a current doubler configuration.
In another aspect, the invention provides a DC/DC voltage converter. The voltage converter comprises an input stage producing first and second alternating cyclic signals and a transformer connected to the input stage. The transformer has an output winding; the output winding has first and second output terminals associated with the first and second alternating cyclic signals. There is also an output stage connected to the transformer. There is also a first transistor having a conduction path associated with the first output terminal and ground for rectifying a first signal present on the first output terminal. The first transistor has a control terminal to regulate a first signal flowing through the conduction path by a first control signal. Also the first transistor has a lower voltage drop in its conduction path than one for a Schottky diode. There is also a first diode associated with the first output terminal for controlling a first ringing signal present on the first signal when the first alternating cyclic signal becomes positive. There is also a second transistor having a second conduction path associated with the second output terminal and the ground for rectifying a second signal present on the second output terminal. The second transistor has a second control terminal to regulate a second signal flowing through the conduction path by a second control signal. Also the second transistor has a lower voltage drop in its conduction path than one for a Schottky diode. A second diode is with the second output terminal for controlling a second ringing signal present on the second signal when the second alternating cyclic signal becomes positive. There is also an energy storage device associated with the first and second clamping means to store energy from the first and second ringing signals.
The DC/DC converter may have a capacitor as the energy storage device and may have FETs for the first and second transistors. Further, the energy stored in the capacitor may be provided to drive the first and second transistors.
The DC/DC converter may further have a third transistor connected in parallel with the first transistor and a fourth transistor connected in parallel with the second transistor. The third transistor is controlled by the first control signal and the fourth transistor is controlled by the second control signal.
The DC/DC converter may have FETs for the third and fourth transistors.
The DC/DC converter may arrange the output winding and the first and second output terminal to be in a center tap configuration.
The DC/DC converter may arrange the output winding and the first and second output terminal in a current doubler configuration.
In a third aspect, the invention provides a method of controlling power loss at an output stage of a DC/DC converter. The output stage of the DC/DC converter has an output winding; the output winding has first and second output terminals; the output stage produces a first alternating cyclic signal on the first output terminal and a second complementary alternating cyclic output signal on the second output terminal. The method comprises controlling a first ringing signal at the first output terminal utilizing a first transistor, controlling a second ringing signal at the second output terminal utilizing a second transistor. Each of the first and second transistors has a lower voltage drop in their conduction path than one for a Schottky diode. The method further comprises clamping a first ringing signal on the first output terminal to a first value, clamping a second ringing signal on the second output terminal to a second value, storing excess energy from the first and second ringing signals in a storage device; and connecting the storage device to control terminals of the first and second transistors.
In other aspects, the invention provides various combinations and subsets of the aspects described above.